One goal on the fabrication of integrated circuitry is to produce a circuit having maximum circuit density. This goal extends to the fabrication of EPROMs. An EPROM is a read only memory device in which the stored data may be erased and new data written in its stead. A widely used type of EPROM is the floating gate field effect transistor type. See Sze, Physics of Semiconductor Devices, Section 8.61 (1981). A partial schematic diagram of an EPROM using floating gate field effect transistors is shown in FIG. 1. Memory cells 26-1-1 through 26-2-4 are floating gate field effect transistors. Row decoder 28 provides output signals on row lines 24-1 and 24-2 in response to signals provided on row address input leads 21 and from read/write indicator 23. Column decoder 29 provides and receives signals on column lines 25-1 through 25-5 in response to signals provided on column address input leads 22 and from read/write indicator 23. A memory output signal is provided on output lead 27. A data bit stored in, for example, memory cell 26-1-1 is read by providing a high voltage output signal on row line 24-1 and providing a low voltage output signal on all other row lines.
Column decoder 29 then senses, via column lines 25-1 and 25-2, the impedance of memory cell 26-1-1. If the floating gate memory of memory cell 26-1-1 contains excess electrons, the negative charge of these excess electrons raises the threshold voltage of memory cell 26-1-1 so that the voltage provided on row line 24-1 is insufficient to cause the channel of memory cell 26-1-1 to conduct. Therefore, column decoder 29 detects a high impedance and provides an appropriate signal on output lead 27. If there are no excess electrons stored on the floating gate on memory cell 26-1-1, then the voltage supplied on row line 24-1 is sufficient to cause memory cell 26-1-1 to conduct. Therefore, column decoder 29 detects a low impedance and provides the appropriate signal on output lead 27.
EPROM 20 is thus programmed by negatively charging the floating gate of selected memory cells. This is accomplished by injecting hot electrons through the insulating layer between the floating gate and the substrate of the memory cell.
Prior art methods of forming floating gate field effect transistors produced field effect transistors having a channel region horizontally disposed in a substrate, an insulator horizontally disposed above the channel, a floating gate horizontally disposed above the insulator, and a control gate insulated from and horizontally disposed above the floating gate